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Publications by Valeriu Codreanu

P Yang, G Clapworthy, F Dong, Codreanu, VB, DP Williams, BQ Liu, JBTM Roerdink, and ZK Deng. GSWO: A Programming Model for GPU-enabled Parallelization of Sliding Window Operations in Image Processing. Signal Processing: Image Communication, 47:332345, 2016.   doi
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M. van der Zwan, V. Codreanu, and A. Telea. CUBu: Universal real-time bundling for large graphs. IEEE Transactions on Visualization and Computer Graphics, 22(12):2250–2263, 2016.   doi
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Valeriu Codreanu, Bob Dröge, David Williams, Burhan Yasar, Po Yang, Baoquan and Dong Liu, Olarik Surinta, Schomaker, Lambert R.B., Jos B.T.M. Roerdink, and Wiering, Marco A.. Evaluating automatically parallelized versions of the support vector machine. Concurrency and Computation: Practice and Experience, 2014.   doi
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Baoquan Liu, Alexandru C. Telea, Jos B.T.M. Roerdink, Gordon J. Clapworthy, David Williams, Po Yang, Feng Dong, Valeriu Codreanu, and Alessandro Chiarini. Parallel Centerline Extraction on the GPU. Computers & Graphics, 41:72–83, 2014.   bib
David Williams, Valeriu Codreanu, Po Yang, Baoquan Liu, Feng Dong, Burhan Yasar, Babak Mahdian, Alessandro Chiarini, Xia Zhao, and Jos B.T.M. Roerdink. Evaluation of autoparallelization toolkits for commodity GPUs. In Parallel Processing and Applied Mathematics. Springer, pages 447–457, 2014.   pdf
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Valeriu Codreanu, Feng Dong, Baoquan Liu, Jos B.T.M. Roerdink, David Williams, Po Yang, and Burhan Yasar. GPU-ASIFT: A Fast Fully Affine-Invariant Feature Extraction Algorithm. In International Conference on High Performance Computing & Simulation 2013, July 1-5, Helsinki, Finland. IEEE, pages 474–481, 2013. Outstanding Paper Runner-up Award at HPCS 2013.   bib
Lucian Petrica, Valeriu Codreanu, and Sorin Cotofana. VASILE: A Reconfigurable Vector Architecture for Instruction Level Frequency Scaling. In 2013 IEEE Faible Tension Faible Consommation, 20-21 June. IEEE, 2013.   bib
Calin Bira, Liviu Gugu, Radu Hobincu, Valeriu Codreanu, Lucian Petrica, and Sorin Cotofana. An Energy Effective SIMD Accelerator for Visual Pattern Matching. In 4th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies 2013, June 13-14. ACM, 2013.   bib
David Williams, Valeriu Codreanu, Jos B.T.M. Roerdink, Po Yang, Baoquan Liu, Feng Dong, and Alessandro Chiarini. Accelerating Colonic Polyp Detection Using Commodity Graphics Hardware. In Proceedings of the International Conference on Computer Medical Applications. Sousse, Tunisia, pages 1–6, 2013.   doi
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Radu Hobincu, Valeriu Codreanu, and Lucian Petrica. GNU Compiler Collection Backend Port For The Integral Parallel Architecture. UPB Scientific Bulletin, 74(3), 2012.   bib
Valeriu Codreanu, David Williams, and Jos B.T.M. Roerdink. A General Toolkit for “GPUtilisation” in SME Applications. In Poster session of the National ICT.OPEN (Rotterdam). October, October 2012.   pdf
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V. Codreanu, L. Petrica, and R. Hobincu. Increasing Vector Processor Pipeline Efficiency with a Thread-interleaved Controller. In System Theory, Control, and Computing (ICSTCC), 2011 15th International Conference on. Pages 1–4, 2011.   bib
V. Codreanu and R. Hobincu. Performance Gain from Data and Control Dependency Elimination in Embedded Processors. In Electronics and Telecommunications (ISETC), 2010 9th International Symposium on. Pages 47–50, 2010.   bib
P. Bumbăcea, V. Codreanu, R. Hobincu, L. Petrică, and GM Ştefan. Technology Driven Architecture for Integral Parallel Embedded Computing. In Semiconductor Conference (CAS), 2010 International. Pages 35–42, 2010.   bib