Multiprocessor synchronization based on locking has well-known scalability problems, and is increasingly recognized as a software engineering quagmire. In response, researchers have spent substantial effort over the years investigating alternatives such as lock-free synchronization. Although modern processors provide primitives powerful enough in principle to support any kind of lock-free synchronization, there is still an inherent performance mismatch between conventional architectures and the kinds of scalable synchronization that will be required by multi-core architectures currently emerging from Intel, AMD, and Sun. This talk considers the prospects for a future in which hardware and software converge on support for a synchronization model based on optimistic, multi-location transactions ("transactional memory").
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