SAAD SALEH received the Master's and Bachelor's degrees in Electrical Engineering with majors in Networks and Communications. Currently, he is doing research on enabling cognitive and energy efficient network functions using Memristor-based in-network processing architectures. This interdisciplinary research is in collaboration with the Groningen Cognitive Systems and Materials Center (CogniGron), The Netherlands.
' 'Saad proposed a novel PCAM abstraction which extends the expressiveness
of current TCAM memory for supporting cognitive functions in the analog domain
with 50 times less energy consumption. The research findings are going to appear
in IEEE INFOCOM 2024 and ACM HotNets 2023.' ' -Bernoulli Newsletter 2023
' ' Saad developed a novel network memory called TCAmMCogniGron for providing computing and cognition with less energy consumption and more robustness in the current network components.' ' -Bernoulli Newsletter 2022
' 'Saad has been awarded the 4TU.NIRICT funding for participation in the European Innovation Academy 2023 at University of Porto, Porto, Portugal.' '
dAQM: Derivative-based Active Queue Management (S. Saleh, S. Shu and B. Koldehofe), In Proceedings of the 23rd International Federation for Information Processing (IFIP) Networking Conference (IFIP NETWORKING 2024), IEEE, 2024.
Current network functions build heavily on fixed programmed rules and lack capacity to support more expressive learning models, e.g. brain-inspired Cognitive computational models using neuromorphic computations. The major reason for this shortcoming is the huge energy consumption and limitation in expressiveness by the underlying TCAM-based digital packet processors. In this research, we show that recent emerging technologies from the analog domain have a high potential in supporting network functions with energy efficiency and more expressiveness, so called cognitive functions. We propose an analog packet processing architecture building on a novel technology named Memristors. We develop a novel analog match-action memory called Probabilistic Content-Addressable Memory (pCAM) for supporting deterministic and probabilistic match functions. We develop the programming abstractions and show the support of pCAM for an active queue management-based analog network function. The analysis over an experimental dataset of a memristor chip showed only 0.01 fJ/bit/cell of energy consumption for corresponding analog computations which is 50 times less than digital computations.
The Internet makes use of high performance network switches in order to route network traffic from end users to servers. Despite line-rate performance, the current switches consume huge energy and cannot support more expressive learning models, like cognitive functions using neuromorphic computations. The major reason is the use of transistors in the underlying Ternary Content-Addressable Memory (TCAM) which is volatile and supports digital computations only. These shortcomings can be bypassed by developing network memories building on novel components, like Memristors, due to their nonvolatile, nanoscale and analog storage/processing characteristics. In this paper, we propose the use of a novel memristor-based Probabilistic Associative Memory, PAmM, which provides both digital (deterministic) and analog (probabilistic) outputs for supporting cognitive computational models in network switches. The traditional digital operations can be supported by a memristor-based energy efficient TCAM, called TCAmMCogniGron. Building on PAmM and TCAmMCogniGron, we propose a novel network switching architecture and analyze its energy efficiency over the experimental dataset of a Nb-doped SrTiO3 memristive device. The results show that the proposed network switching architecture consumes only 0.01 fJ/bit/cell energy for analog compute operations which is at least 50 times less than the digital operations.
The high performance requirements of nowadays computer networks are limiting their ability to support important requirements of the future. Two important properties essential in assuring cost-efficient computer networks and supporting new challenging network scenarios are operating energy efficient and supporting cognitive computational models. These requirements are hard to fulfill without challenging the current architecture behind network packet processing elements such as routers and switches. Notably, these are currently dominated by the use of traditional transistor-based components. In this article, we contribute with an in-depth analysis of alternative architectural design decisions to improve the energy footprint and computational capabilities of future network packet processors by shifting from transistor-based components to a novel component named Memristor . A memristor is a computational component characterized by non-volatile operations on a physical state, mostly represented in form of (electrical) resistance. Its state can be read or altered by input signals, e.g. electrical pulses, where the future state always depends on the past state. Unlike in traditional von Neumann architectures, the principles behind memristors impose that memory operations and computations are inherently colocated. In combination with the non-volatility, this allows to build memristors at nanoscale size and significantly reduce the energy consumption. At the same time, memristors appear to be highly suitable to model cognitive functionality due to the state dependence transitions in the memristor. In cognitive architectures, our survey contributes to the study of memristor-based Ternary Content Addressable Memory (TCAM) used for storage of cognitive rules inside packet processors. Moreover, we analyze the memristor-based novel cognitive computational architectures built upon self-learning capabilities by harnessing from non-volatility and state-based response of memristors (including reconfigurable architectures, reservoir computation architectures, neural network architectures and neuromorphic computing architectures).
The Internet relies heavily on programmable match-action processors for matching network packets against locally available network rules and taking actions, such as forwarding and modification of network packets. This match-action process must be performed at high speed, i.e., commonly within one clock cycle, using a specialized memory unit called Ternary Content Addressable Memory (TCAM). Building on transistor-based CMOS designs, state-of-the-art TCAM architectures have high energy consumption and lack resilient designs for incorporating novel technologies for performing appropriate actions. In this article, we motivate the use of a novel fundamental component, the ‘Memristor’, for the development of TCAM architecture for match-action processing. Memristors can provide energy efficiency, non-volatility and better resource density as compared to transistors. We have proposed a novel memristor-based TCAM architecture called TCAmMCogniGron, built upon the voltage divider principle and requiring only two memristors and five transistors for storage and search operations compared to sixteen transistors in the traditional TCAM architecture. We analyzed its performance over an experimental data set of Nb-doped SrTiO3-based memristor. The analysis of TCAmMCogniGron showed promising power consumption statistics of 16 uW and 1 uW for match and mismatch operations along with twice the improvement in resources density as compared to the traditional architectures.
Match-action processors play a crucial role of communicating end-users in the Internet by computing network paths and enforcing administrator policies. The computation process uses a specialized memory called Ternary Content Addressable Memory (TCAM) to store processing rules and use header information of network packets to perform a match within a single clock cycle. Currently, TCAM memories consume huge amounts of energy resources due to the use of traditional transistor-based CMOS technology. In this article, we motivate the use of a novel component, the memristor, for the development of a TCAM architecture. Memristors can provide energy efficiency, non-volatility, and better resource density as compared to transistors. We have proposed a novel memristor-based TCAM architecture built upon the voltage divider principle for energy efficient match-action processing. Moreover, we have tested the performance of the memristor-based TCAM architecture using the experimental data of a novel Nb-doped SrTiO3 memristor. Energy analysis of the proposed TCAM architecture for given memristor shows promising power consumption statistics of 16 μW for a match operation and 1 μW for a mismatch operation.
Please find more detailed information about the Projects, Research, Teaching and Supervision activities of Saad Saleh at the official RUG profile page or saadsaleh.github.io.
' ' Can Memristors Reduce the Carbon Footprint of the Internet?' ' -DSOS Blog
